The Hidden Truth About Instruction Set Emulators and the Circuit-Level PDP-11/34 Emulator
Most emulators abstract away the messy details, much like a high-level language. They execute instructions, but ignore the underlying hardware's reality. UNIBUS contention can stall an instruction, or subtle timing quirks can introduce real-world bugs. An instruction-set emulator, however, simply reports "instruction complete" without exposing these underlying issues. A circuit-level PDP-11/34 emulator, like ll/34, exposes the actual bus signals, clock cycles, and microcode steps. This is the difference between a simulation and a digital replica, a distinction crucial for a true circuit-level PDP-11/34 emulator.
This project began as a debugging tool for a *physical* PDP-11/34A. Its purpose wasn't to run V6 UNIX faster, but to diagnose why a real machine was failing. That's engineering discipline. The developers didn't guess; they reverse-engineered schematics, microcode, and logic captures from an actual system. This approach reveals the true failure modes, not just the expected outcomes.
The KD11-EA: A Digital Replica of the PDP-11/34
The core of ll/34 is its virtual KD11-EA CPU, forming the heart of this circuit-level PDP-11/34 emulator. This isn't an abstract model; it's a direct C translation of the original schematics. Every 74xx gate is simulated using C logic operators. This design ensures that if a physical PDP-11/34 had a specific hardware bug, ll/34 will reproduce it. That's the entire point: ignoring these failure modes in emulation means missing critical debugging opportunities and a complete understanding of the system's behavior. This fidelity is what defines a circuit-level PDP-11/34 emulator.
The implementation details are critical for understanding how a circuit-level PDP-11/34 emulator achieves its precision:
- Microcode Store (
ucode_rom.h): This 512x48-bit bipolar PROM dictates the CPU's fundamental operations. It controls the ALU, scratchpad, bus interface, and branching for each micro-cycle. Precise emulation of this store is critical because it defines the instruction set's execution semantics and potential micro-architectural quirks, based on Bitsavers Verilog and actual dumps from a working PDP-11/34A. - Combinational ROMs (
combo_roms.h): These ROMs are not merely memory; they implement critical logic functions. Specifically, E51-E83 and E107 manage instruction register (IR) decode, ALU function selection, trap/service priority, and condition codes. Their exact replication, including open-collector ROMs wire-ORing onto the MPC bus, is essential for reproducing the precise control flow and potential race conditions inherent in the original hardware, reconstituted from reverse-engineered schematics and logic captures. - Datapath Engine (
kd11ea.c): This engine executes microcode steps, processing one micro-word per cycle. Its full model of the 74S181 bit-slice ALU, including all four slices for complete 16-bit operations, is crucial for accurately reflecting the CPU's arithmetic and logic behavior, including any carry propagation or overflow characteristics. - Memory Management (
mmu.c): This unit precisely replicates the original memory protection and address translation. It handles kernel/user address spaces, 18-bit relocation via three 74S283 adders, 16 PAR/PDR pairs, and SR0/SR2 abort registers with their freeze logic. Accurate MMU emulation is vital for reproducing memory access violations, protection faults, and the exact address translation behavior that can expose subtle software bugs. - Clock Generator (
clockgen.c): This is far more than a simple timer; it models the E106 delay line, including TAP 30/90/120 feedback and TRAN INH bus wait. With short cycles at 180 ns and long cycles at 240 ns, and bus transfers extending until SSYN returns, this precise timing accuracy is paramount. It is fundamental to reproducing the exact micro-timing dependencies that can lead to real-world hardware and software synchronization issues, and without it, the circuit-level PDP-11/34 emulator fails its core purpose.
Debugging: Beyond the Instruction Set with the ll/34 Emulator
While ll/34 includes sample programs like V6 UNIX and RT-11 V4 (with original Tetris game), its primary purpose is not merely running old games. The ll/34 includes a programmer console that emulates the front panel switches and indicators. This allows bus initialization, booting, single-stepping, and examine/deposit data. While the programmer console offers basic interaction, the real power of ll/34 emerges with its debug console and integrated logic analyzer.
The debug console enables single-stepping of micro-instructions, PC breakpoints, memory dumps, MMU state inspection, instruction disassembly, and register dumps. This provides debugging capabilities at both the instruction and microcode levels.
Then there's the logic analyzer (Ctrl-L). This is the most significant feature. It probes 102 major CPU signals, mapped directly to physical chip pins using the KD1:Exx:pin notation (referencing the board, module, and pin number as per DEC schematics). Users can capture up to 64K samples at the actual CPU clock rate (5,555,556 Hz, 180 ns resolution), trigger on any signal, and export data to CSV. This isn't just for virtual debugging; it's a tool capable of troubleshooting a *physical* PDP-11/34, highlighting the critical importance of signal integrity in such systems, a core strength of the circuit-level PDP-11/34 emulator.
The Real Value of Circuit-Level PDP-11/34 Emulation
Projects like ll/34 are critical because they preserve not just software, but fundamental *hardware knowledge*. They offer a tangible way to understand computing's foundational principles, moving beyond abstract concepts to interacting circuits. By observing the causal link between a microcode instruction and UNIBUS state changes, one can truly reveal the mechanics of early computing, including its inherent failure modes. This is the essence of a circuit-level PDP-11/34 emulator.
This isn't a replacement for FPGA-based emulation, which offers distinct advantages in raw performance and direct hardware interaction. However, ll/34's circuit-level C implementation was specifically chosen over gate-level Verilog to reproduce subtle hardware bugs while maintaining execution speed, a critical balance for its diagnostic purpose. It provides an accessible, granular analysis tool. Its value lies in education, historical accuracy, and practical hardware diagnostics, offering unparalleled insight into the system's true operational mechanics.
